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128k x 32 synchronous-flow-through 3.3v cache ram cy7c1338b cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 january 18, 2001 features ? supports 117-mhz microprocessor cache systems with zero wait states 128k by 32 common i/o fast clock-to-output times ? 7.5 ns (117-mhz version) two-bit wraparound counter supporting either inter- leaved or linear burst sequence separate processor and controller address strobes pro- vide direct interface with the processor and external cache controller synchronous self-timed write asynchronous output enable 3.3v/ 2.5v i/os jedec-standard pinout 100-pin tqfp packaging zz ?sleep? mode available in commercial and industrial temperatures functional description the cy7c1338b is a 3.3v, 128k by 32 synchronous cache ram designed to interface with high-speed microprocessors with minimum glue logic. maximum access delay from clock rise is 7.5 ns (117-mhz version). a 2-bit on-chip counter cap- tures the first address in a burst and increments the address automatically for the rest of the burst access. the cy7c1338b allows both interleaved and linear burst se- quences, selected by the mode input pin. a high selects an interleaved burst sequence, while a low selects a linear burst sequence. burst accesses can be initiated with the processor address strobe (adsp ) or the cache controller address strobe (adsc ) inputs. address advancement is controlled by the address advancement (adv ) input. a synchronous self-timed write mechanism is provided to sim- plify the write interface. a synchronous chip enable input and an asynchronous output enable input provide easy control for bank selection and output three-state control. selection guide -117 -100 maximum access time (ns) 7.5 8.0 maximum operating current (ma) 350 325 maximum standby current (ma) 2.0 2.0 pentium is a registered trademark of intel corporation. clk adv adsc a [16:0] gw bwe bw 0 ce 1 ce 3 ce 2 oe zz burst counter dq[31:24] bytewrite registers address register d q input registers 128k x 32 memory array clk q 0 q 1 q d ce ce clr sleep control dq[23:16] bytewrite registers d q dq dq[15:8] bytewrite registers dq[7:0] bytewrite registers d q enable register d q ce clk 32 32 17 15 15 17 (a 0 ,a 1 ) 2 mode adsp logic block diagram dq [31:0] bw 1 bw 2 bw 3
cy7c1338b 2 pin configurations a 5 a 4 a 3 a 2 a 1 a 0 nc nc v ss v dd nc nc a 10 a 11 a 12 a 13 a 14 a 15 a 16 nc dq 15 dq 14 v ddq v ssq dq 13 dq 12 dq 11 dq 10 v ssq v ddq dq 9 dq 8 v ss nc v dd zz dq 7 dq 6 v ddq v ssq dq 5 dq 4 dq 3 dq 2 v ssq v ddq dq 1 dq 0 nc nc dq 16 dq 17 v ddq v ssq dq 18 dq 19 dq 20 dq 21 v ssq v ddq dq 22 dq 23 nc v dd nc v ss dq 24 dq 25 v ddq v ssq dq 26 dq 27 dq 28 dq 29 v ssq v ddq dq 30 dq 31 nc a6 a7 ce 1 ce 2 bw 3 bw 2 bw 1 bw 0 ce 3 v dd v ss clk gw bwe oe adsc adsp adv a 8 a 9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 mode byte0 byte1 byte3 byte2 100-pin tqfp cy7c1338b
cy7c1338b 3 pin descriptions name i/o description adsc input- synchronous address strobe from controller, sampled on the rising edge of clk. when asserted low, a [16:0] is captured in the address registers. a [1:0] are also loaded into the burst counter. when adsp and adsc are both asserted, only adsp is recognized. adsp input- synchronous address strobe from processor, sampled on the rising edge of clk. when asserted low, a [16:0] is captured in the address registers. a [1:0] are also loaded into the burst counter. when adsp and adsc are both asserted, only adsp is recognized. asdp is ignored when ce 1 is deasserted high. a [1:0] input- synchronous a 1 , a 0 address inputs. these inputs feed the on-chip burst counter as the lsbs as well as being used to access a particular memory location in the memory array. a [16:2] input- synchronous address inputs used in conjunction with a [1:0] to select one of the 64k address locations. sampled at the rising edge of the clk, if ce 1 , ce 2 , and ce 3 are sampled active, and adsp or adsc is active low. bw [3:0] input- synchronous byte write select inputs, active low. qualified with bwe to conduct byte writes. sampled on the rising edge. bw 0 controls dq [7:0] and dp 0 , bw 1 controls dq [15:8] and dp 1 , bw 2 controls dq [23:16] and dp 2 , and bw 3 controls dq [31:24] and dp 3 . see write cycle descriptions table for further details. adv input- synchronous advance input used to advance the on-chip address counter. when low the internal burst counter is advanced in a burst sequence. the burst sequence is selected using the mode input. bwe input- synchronous byte write enable input, active low. sampled on the rising edge of clk. this signal must be asserted low to conduct a byte write. gw input- synchronous global write input, active low. sampled on the rising edge of clk. this signal is used to conduct a global write, independent of the state of bwe and bw [3:0] . global writes override byte writes. clk input-clock clock input. used to capture all synchronous inputs to the device. ce 1 input- synchronous chip enable 1 input, active low. sampled on the rising edge of clk. used in conjunction with ce 2 and ce 3 to select/deselect the device. ce 1 gates adsp . pin configurations (continued) 234 567 1 a b c d e f g h j k l m n p r t u v ddq nc nc nc dq c dq d dq c dq d aa aa adsp v ddq ce 2 a dq c v ddq dq c v ddq v ddq v ddq dq d dq d nc nc v ddq v dd clk v dd v ss v ss v ss v ss v ss v ss v ss v ss nc nc nc v dd tdo tck tdi tms nc nc nc v ddq v ddq v ddq aa a a nc a a a a a a a0 a1 dq a dq c dq a dq a dq a dq b dq b dq b dq b dq b dq b dq b dq a dq a dq a dq a dq b v dd dq c dq c dq c v dd dq d dq d dq d dq d adsc nc ce 1 oe adv gw v ss v ss v ss v ss v ss v ss v ss v ss nc mode nc nc bw b bw c nc v dd nc bw a nc bwe bw d zz cy7c1338b (128k x 32) 119-ball bga
cy7c1338b 4 functional overview all synchronous inputs pass through input registers controlled by the rising edge of the clock. maximum access delay from the clock rise (t cdv ) is 7.5 ns (117-mhz device). the cy7c1338b supports secondary cache in systems utiliz- ing either a linear or interleaved burst sequence. the inter- leaved burst order supports pentium and i486 processors. the linear burst sequence is suited for processors that utilize a linear burst sequence. the burst order is user selectable, and is determined by sampling the mode input. accesses can be initiated with either the processor address strobe (adsp ) or the controller address strobe (adsc ). address advancement through the burst sequence is controlled by the adv input. a two-bit on-chip wraparound burst counter captures the first ad- dress in a burst sequence and automatically increments the address for the rest of the burst access. byte write operations are qualified with the byte write enable (bwe ) and byte write select (bw [3:0] ) inputs. a global write enable (gw ) overrides all byte write inputs and writes data to all four bytes. all writes are simplified with on-chip synchro- nous self-timed write circuitry. three synchronous chip selects (ce 1 , ce 2 , ce 3 ) and an asynchronous output enable (oe ) provide for easy bank se- lection and output three-state control. adsp is ignored if ce 1 is high. single read accesses a single read access is initiated when the following conditions are satisfied at clock rise: (1) ce 1 , ce 2 , and ce 3 are all as- serted active, and (2) adsp or adsc is asserted low (if the access is initiated by adsc , the write inputs must be deassert- ed during this first cycle). the address presented to the ad- dress inputs is latched into the address register and the burst counter/control logic and presented to the memory core. if the oe input is asserted low, the requested data w ill be available at the data outputs a maximum to t cdv after clock rise. adsp is ignored if ce 1 is high. single write accesses initiated by adsp this access is initiated when the following conditions are sat- isfied at clock rise: (1) ce 1 , ce 2 , and ce 3 are all asserted active, and (2) adsp is asserted low. the addresses pre- sented are loaded into the address register and the burst counter/control logic and delivered to the ram core. the write inputs (gw , bwe , and bw [3:0] ) are ignored during this first clock cycle. if the write inputs are asserted active (see write cycle descriptions table for appropriate states that indicate a write) on the next clock rise, the appropriate data will be latched and written into the device. byte writes are allowed. during byte writes, bw 0 controls dq [7:0] , bw 1 controls dq [15:8] , bw 2 controls dq [23:16] , and bw 3 controls dq [31:24] . all i/os are three-stated during a byte write. since this is a common i/o device, the asynchronous oe input signal must be deasserted and the i/os must be three-stated prior to the presentation of data to dq [31:0] . as a safety precaution, the ce 2 input- synchronous chip enable 2 input, active high. sampled on the rising edge of clk. used in conjunction with ce 1 and ce 3 to select/deselect the device. ce 3 input- synchronous chip enable 3 input, active low. sampled on the rising edge of clk. used in conjunction with ce 1 and ce 2 to select/deselect the device. oe input- asynchronous output enable, asynchronous input, active low. controls the direction of the i/o pins. when low, the i/o pins behave as outputs. when deasserted high, i/o pins are three-stated, and act as input data pins. zz input- asynchronous snooze input. active high asynchronous. when high, the device enters a low-power standby mode in which all other inputs are ignored, but the data in the memory array is maintained. leaving zz floating or nc will default the device into an active state. zz pin has an internal pull-down. mode - mode input. selects the burst order of the device. tied high selects the interleaved burst order. pulled low selects the linear burst order. when left floating or nc, defaults to interleaved burst order. mode pin has an internal pull-up. dq [31:0] i/o- synchronous bidirectional data i/o lines. as inputs, they feed into an on-chip data register that is triggered by the rising edge of clk. as outputs, they deliver the data contained in the memory location specified by a [16:0] during the previous clock rise of the read cycle. the direction of the pins is controlled by oe in conjunction with the internal control logic. when oe is asserted low, the pins behave as outputs. when high, dq [31:0] and dp [3:0] are placed in a three-state condition. the outputs are automatically three-stated when a write cycle is detected. v dd power supply power supply inputs to the core of the device. should be connected to 3.3v power supply. v ss ground ground for the i/o circuitry of the device. should be connected to ground of the system. v ssq ground ground for the device. should be connected to ground of the system. v ddq i/o power supply power supply for the i/o circuitry. should be connected to a 3.3v power supply. nc - no connects. dnu - do not use pins. should be left unconnected or tied low. pin descriptions (continued) name i/o description
cy7c1338b 5 data lines are three-stated once a write cycle is detected, re- gardless of the state of oe . single write accesses initiated by adsc this write access is initiated when the following conditions are satisfied at clock rise: (1) ce 1 , ce 2 , and ce 3 are all asserted active, (2) adsc is asserted low, (3) adsp is deasserted high, and (4) the write input signals (gw , bwe , and bw [3:0] ) indicate a write access. adsc is ignored if adsp is active low. the addresses presented are loaded into the address register and the burst counter/control logic and delivered to the ram core. the information presented to dq [31:0] will be written into the specified address location. byte writes are allowed. during byte writes, bw 0 controls dq [7:0] , bw 1 controls dq [15:8] , bw 2 controls dq [23:16] , and bws 3 controls dq [31:24] . all i/os are three-stated when a write is detected, even a byte write. since this is a common i/o device, the asynchronous oe input signal must be deasserted and the i/os must be three-stated prior to the presentation of data to dq [31:0] . as a safety precaution, the data lines are three-stated once a write cycle is detected, re- gardless of the state of oe . burst sequences the cy7c1338b provides an on-chip 2-bit wraparound burst counter inside the sram. the burst counter is fed by a [1:0] , and can follow either a linear or interleaved burst order. the burst order is determined by the state of the mode input. a low on mode will select a linear burst sequence. a high on mode will select an interleaved burst order. leaving mode unconnected will cause the device to default to an interleaved burst sequence. sleep mode the zz input pin is an asynchronous input. asserting zz high places the sram in a power conservation ? sleep ? mode. two clock cycles are required to enter into or exit from this ? sleep ? mode. while in this mode, data integrity is guaranteed. ac- cesses pending when entering the ? sleep ? mode are not con- sidered valid nor is the completion of the operation guaran- teed. the device must be deselected prior to entering the ? sleep ? mode. ce 1 , ce 2 , ce 3 , adsp , and adsc must remain inactive for the duration of t zzrec after the zz input returns low. leaving zz unconnected defaults the device into an ac- tive state. table 1. counter implementation for the intel pentium ? /80486 processor ? s sequence first address second address third address fourth address a x + 1 , a x a x + 1 , a x a x + 1 , a x a x + 1 , a x 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 table 2. counter implementation for a linear sequence first address second address third address fourth address a x + 1 , a x a x + 1 , a x a x + 1 , a x a x + 1 , a x 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 zz mode electrical characteristics parameter description test conditions min. max. unit i cczz snooze mode standby current zz > v dd ? 0.2v 10 ma t zzs device operation to zz zz > v dd ? 0.2v 2t cyc ns t zzrec zz recovery time zz < 0.2v 2t cyc ns
cy7c1338b 6 cycle description table [1, 2, 3] cycle description add used ce 1 ce 3 ce 2 zz adsp adsc adv we oe clk dq deselected cycle, power-down none h x x l x l x x x l-h high-z deselected cycle, power-down none l x l l l x x x x l-h high-z deselected cycle, power-down none l h x l l x x x x l-h high-z deselected cycle, power-down none l x l l h l x x x l-h high-z deselected cycle, power-down none x x x l h l x x x l-h high-z snooze mode, power-down none x x x h x x x x x x high-z read cycle, begin burst external l l h l l x x x l l-h q read cycle, begin burst external l l h l l x x x h l-h high-z write cycle, begin burst external l l h l h l x l x l-h d read cycle, begin burst external l l h l h l x h l l-h q read cycle, begin burst external l l h l h l x h h l-h high-z read cycle, continue burst next x x x l h h l h l l-h q read cycle, continue burst next x x x l h h l h h l-h high-z read cycle, continue burst next h x x l x h l h l l-h q read cycle, continue burst next h x x l x h l h h l-h high-z write cycle, continue burst next x x x l h h l l x l-h d write cycle, continue burst next h x x l x h l l x l-h d read cycle, suspend burst current x x x l h h h h l l-h q read cycle, suspend burst current x x x l h h h h h l-h high-z read cycle, suspend burst current h x x l x h h h l l-h q read cycle, suspend burst current h x x l x h h h h l-h high-z write cycle, suspend burst current x x x l h h h l x l-h d write cycle, suspend burst current h x x l x h h l x l-h d notes: 1. x = ? don't care, ? 1 = logic high, 0 = logic low. 2. the sram always initiates a read cycle when adsp asserted, regardless of the state of gw , bwe , or bws [3:0]. writes may occur only on subsequent clocks after the adsp or with the assertion of adsc . as a result, oe must be driven high prior to the start of the write cycle to allow the outputs to three-state. oe is a ? don't care ? for the remainder of the write cycle. 3. oe is asynchronous and is not sampled with the clock rise. during a read cycle dq = high-z when oe is inactive, and dq = data when oe is active.
cy7c1338b 7 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................... ? 65 c to +150 c ambient temperature with power applied ............................................... ? 55 c to +125 c supply voltage on v dd relative to gnd................ ? 0.5v to +4.6v dc voltage applied to outputs in high z state [5] ............................................... ? 0.5v to v dd + 0.5v dc input voltage [5] ........................................... ? 0.5v to v dd + 0.5v current into outputs (low)......................................... 20 ma static discharge voltage .......................................... >2001v (per mil-std-883, method 3015) latch-up current.................................................... >200 ma notes: 4. when a write cycle is detected, all i/os are three-stated, even during byte writes. 5. minimum voltage equals ? 2.0v for pulse durations of less than 20 ns. 6. t a is the case temperature. write cycle descriptions [1, 2, 3, 4] function gw bwe bw 3 bw 2 bw 1 bw 0 read 1 1xxxx read 101111 write byte 0 - dq [7:0] 101110 write byte 1 - dq [15:8] 101101 write bytes 1, 0 101100 write byte 2 - dq [23:16] 101011 write bytes 2, 0 101010 write bytes 2, 1 101001 write bytes 2, 1, 0 101000 write byte 3 - dq [31:24] 100111 write bytes 3, 0 100110 write bytes 3, 1 100101 write bytes 3, 1, 0 100100 write bytes 3, 2 100011 write bytes 3, 2, 0 100010 write bytes 3, 2, 1 100001 write all bytes 100000 write all bytes 0 xxxxx operating range range ambient temperature [6] v dd v ddq com ? l 0 c to +70 c 3.135v to 3.6v 2.375v to v dd ind ? l ? 40 c to +85 c
cy7c1338b 8 electrical characteristics over the operating range parameter description test conditions min. max. unit v oh output high voltage v ddq = 3.3v, v dd = min., i oh = ? 4.0 ma 2.4 v v ddq = 2.5v, v dd = min., i oh = ? 2.0 ma 2.0 v v ol output low voltage v ddq = 3.3v, v dd = min., i ol = 8.0 ma 0.4 v v ddq = 2.5v, v dd = min., i ol = 2.0 ma 0.7 v v ih input high voltage v ddq = 3.3v 2.0 v dd + 0.3v v v ih input high voltage v ddq = 2.5v 1.7 v dd + 0.3v v v il input low voltage [5] v ddq = 3.3v ? 0.3 0.8 v v il input low voltage [5] v ddq = 2.5v ? 0.3 0.7 v i x input load current (except zz and mode) gnd v i v ddq ? 11 a input current of mode input = v ss ? 30 a input = v ddq 5 a input current of zz input = v ss ? 5 a input = v ddq 30 a i oz output leakage current gnd v i v dd, output disabled ? 55 a i os output short circuit current [7] v dd = max., v out = gnd ? 300 ma i dd v dd operating supply current v dd = max., i out = 0 ma, f = f max =1/t cyc 8.5-ns cycle, 117 mhz 350 ma 10-ns cycle, 100 mhz 325 ma i sb1 automatic ce power-down current ? ttl inputs max. v dd , device deselected, v in v ih or v in v il , f = f max = 1/t cyc , inputs switching 8.5-ns cycle, 117 mhz 125 ma 10-ns cycle, 100 mhz 110 ma i sb2 automatic ce power-down current ? cmos inputs max. v dd , device deselected, v in 0.3v or v in > v ddq ? 0.3v, f = 0, inputs static all speeds 10 ma i sb3 automatic ce power-down current ? cmos inputs max. v dd , device deselected, v in v ddq ? 0.3v or v in 0.3v, f = f max , inputs switching 8.5-ns cycle, 117 mhz 95 ma 10-ns cycle, 100 mhz 85 ma i sb4 automatic ce power-down current ? cmos inputs max. v dd , device deselected, v in v dd ? 0.3v or v in 0.3v, f = 0, inputs static all speeds 30 ma note: 7. not more than one output should be shorted at one time. duration of the short circuit should not exceed 30 seconds.
cy7c1338b 9 capacitance [8] parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v dd = 5.0v 5.0 pf c i/o i/o capacitance 8.0 pf ac test loads and waveforms 3.0v gnd 90% 10% 90% 10% 3.0 ns 3.0 ns output r1=317 ? r2=351 ? 5pf including jig and scope (a) (b) all input pulses output r l =50 ? z 0 =50 ? v l =1.5v 3.3v switching characteristics over the operating range [9] parameter description -117 -100 min. max. min. max. unit t cyc clock cycle time 8.5 10 ns t ch clock high 3.0 4.0 ns t cl clock low 3.0 4.0 ns t as address set-up before clk rise 1.5 1.5 ns t ah address hold after clk rise 0.5 0.5 ns t cdv data output valid after clk rise 7.5 8.0 ns t doh data output hold after clk rise 2.0 2.0 ns t ads adsp , adsc set-up before clk rise 2.0 2.0 ns t adh adsp , adsc hold after clk rise 0.5 0.5 ns t wes bws [1:0] , gw ,bwe set-up before clk rise 2.0 2.0 ns t weh bws [1:0] , gw ,bwe hold after clk rise 0.5 0.5 ns t advs adv set-up before clk rise 2.0 2.0 ns t advh adv hold after clk rise 0.5 0.5 ns t ds data input set-up before clk rise 1.5 1.5 ns t dh data input hold after clk rise 0.5 0.5 ns t ces chip enable set-up 2.0 2.0 ns t ceh chip enable hold after clk rise 0.5 0.5 ns t chz clock to high-z [10, 11] 3.5 3.5 ns t clz clock to low-z [10, 11] 00ns t eohz oe high to output high-z [10, 12] 3.5 3.5 ns t eolz oe low to output low-z [10, 12] 00ns t eov oe low to output valid 3.5 3.5 ns notes: 8. tested initially and after any design or process changes that may affect these parameters. 9. unless otherwise noted, test conditions assume signal transition time of 2.5 ns or less, timing reference levels of 1.25v, in put pulse levels of 0 to 2.5v, and output loading of the specified i ol /i oh and load capacitance. shown in (a) and (b) of ac test loads. 10. t chz , t clz , t eohz , and t eolz are specified with a load capacitance of 5 pf as in part (b) of ac test loads. transition is measured 200 mv from steady-state voltage. 11. at any given voltage and temperature, t chz (max) is less than t clz (min). 12. this parameter is sampled and not 100% tested.
cy7c1338b 10 timing diagrams write cycle timing [13, 14] notes: 13. we is the combination of bwe , bw [3:0] , and gw to define a write cycle (see write cycle descriptions table). 14. wdx stands for write data to address x. adsp clk adsc adv add ce 1 oe gw we ce 2 ce 3 1a data in t cyc t ch t cl t ads t adh t ads t adh t advs t advh wd1 wd2 wd3 t ah t as t ws t wh t wh t ws t ces t ceh t ces t ceh t ces t ceh 2b 3a 1a single w rite burst write unselected adsp ignored with ce 1 inactive ce 1 masks adsp = don ? t care = undefined pipelined write 2a 2c 2d t dh t ds high-z high-z unselected with ce 2 adv must be inactive for adsp write adsc initiated write
cy7c1338b 11 read cycle timing [13, 15] note: 15. rdx stands for read data from address x. timing diagrams (continued) adsp clk adsc adv add ce 1 oe gw we ce 2 ce 3 2a 2c 1a data out t cyc t ch t cl t ads t adh t ads t adh t advs t advh rd1 rd2 rd3 t ah t as t ws t wh t wh t ws t ces t ceh t ces t ceh t ces t ceh t cdv t eov 2b 2c 2d 3a 1a t oehz t doh t clz t chz single read burst read unselected adsp ignored with ce 1 inactive suspend burst ce 1 masks adsp = don ? t care = undefined pipelined read adsc initiated read unselected with ce 2
cy7c1338b 12 read/write cycle timing timing diagrams (continued) a t ah t as we is the combination of bwe , bws [1:0] , and gw to define a write cycle (see write cycle descriptions table). t clz t chz ce is the combination of ce 2 and ce 3 . all chip selects need to be active in order to select the device. rax stands for read address x, wax stands for write address x, dx stands for data-in x, t doh clk add we ce 1 data b c d adsp adsc adv ce oe q(a) q(b) q (b+1) q (b+2) q (b+3) q(b) d(c) d (c+1) d (c+2) d (c+3) q(d) t cyc t ch t cl t ads t adh t ads t adh t advh t advs t ceh t ceh t ces t ces t weh t wes t cdv device originally deselected adsp ignored with ce 1 high t eohz qx stands for data-out x. in/out
cy7c1338b 13 timing diagrams (continued) in/out a t as = don ? t care = undefined we is the combination of bwe , bw [1:0] , and gw to define a write cycle (see write cycle descriptions table). t clz t chz ce is the combination of ce 2 and ce 3 . all chip selects need to be active in order to select the device. rax stands for read address x, wax stands for write address x, dx stands for data-in x, t doh clk add we ce 1 data b adsp adsc adv ce oe q(a) q(b) q(d) d(c) d (e) d (f) d (g) t cyc t ch t cl t ads t adh t ceh t ces t weh t wes t cdv pipeline timing device originally deselected adsp ignored with ce 1 high qx stands for data-out x. c d q(c) ef gh d (h)
cy7c1338b 14 timing diagrams (continued) oe three-state i/os t eohz t eov t eolz oe switching waveforms
cy7c1338b 15 notes: 16. device must be deselected when entering zz mode. see cycle descriptions table for all possible signal conditions to deselect the device. 17. i/os are in three-state when exiting zz ? sleep ? mode. timing diagrams (continued) adsp clk adsc ce 1 ce 3 low high zz t zzs t zzrec i cc i cc (active) three-state i/os zz mode timing [16, 17] ce 2 i cczz high
cy7c1338b 16 document #: 38-00939-*c ordering information speed (mhz) ordering code package name package type operating range 117 cy7c1338b-117ac a101 100-lead thin quad flat pack commercial CY7C1338B-117BGC bg119 119-ball bga 100 cy7c1338b-100ac a101 100-lead thin quad flat pack cy7c1338b-100bgc bg119 119-ball bga cy7c1338b-100ai a101 100-lead thin quad flat pack industrial cy7c1338b-100bgi bg119 119-ball bga package diagrams 100-pin thin plastic quad flatpack (14 x 20 x 1.4 mm) a101 51-85050-a
cy7c1338b ? cypress semiconductor corporation, 2001. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. package diagrams (continued) 119-lead fbga (14 x 22 x 2.4 mm) bg119 51-85115

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